FIELD OF THE INVENTION
The invention relates to a circuit configuration for reducing injection of minority carriers into a substrate containing regions forming a pn junction, including a transistor connected to an external terminal of the circuit configuration.
Integrated semiconductor circuits contain a substrate, in which respective p-doped and n-doped regions are embedded with a predetermined structure. For example, n-doped wells which receive electrical components may be disposed on a p-type substrate. The pn junction with the substrate must always be reverse-biased so that no minority carriers are injected into the substrate. Such minority carriers spread by diffusion and, if they reach other circuit elements, cause malfunctions because of their parasitic properties. For that reason, on one hand the substrate is typically connected to the lowest potential of the circuit. On the other hand it is known that external connections to the integrated circuit entail problems with the circuit. The external terminals of the circuit, in particular the inputs and outputs of the circuit, therefore constitute particularly critical points.
If the current flowing through them is interrupted suddenly, loads which have an inductive component can produce a back-emf. Other problems are also possible, for example resulting from changes in the supply voltage. The effects result in a minority carrier current being injected into the substrate and being on the order of magnitude of the working current through a transistor. The back of the chip and the wells over the substrate act as sinks for the charge carriers. The motion of the minority carriers due to the concentration gradient causes so-called transverse currents. Only a fraction of the minority carriers combines in the substrate, since the crystalline quality of the substrate is generally so good that only low recombination rates, that is to say long carrier lifetimes, occur. The component wells of the circuit must therefore take up large transverse currents, which leads to undesired activation of parasitic bipolar transistors and therefore to malfunctions.
Published European Patent Application 0 284 979 A1 discloses a substrate which in each case is connected through a diode to the external terminal, or to a reference terminal for connection to a reference potential. In addition, German Published, Non-prosecuted Patent Application DE 44 11 869 A1, corresponding to allowed U.S. application Ser. No. 08/417,825, filed Apr. 6, 1995, discloses that a heavily doped substrate having an overlying weakly doped layer of the same conductivity is used, and that the wells are surrounded by a protective ring. Although that measure does not actually impede the injection of minority carriers, it greatly restricts the spreading of the charge carriers. Furthermore, a measure of that type is only of very limited effect in typical bipolar technologies, since substrates having epitaxial layers as in MOS technologies are not used.
Published European Patent Application 0 409 158 A1, corresponding to U.S. Pat. No. 3,058,428, discloses a circuit configuration for reducing injection of minority carriers into a substrate, in which a control loop, including a comparator and a transistor, is formed in conjunction with a working circuit.